Rabaey J, Chandrakasan A, Nikolic B “Digital integrated circuits a design perspective”. From Fig.5, it has been observed that in between 1 Volt and 1.2 Volt of VDD, at 0.6 V, 0.7 V and 0.9 V PDPs are supposed to be optimum. The graphical variation of PDP is shown in Fig.5. To get the optimum value of VDD, the PDP has been calculated. 3 and 4, it is contradictory regarding the value of VDD for which the performance is acceptable. It is found that, the gate delay decreases for the higher value of VDD. The graphical variation of delay is shown in Fig.4. Therefore, to reduce the power consumption the VDD needs to be scaled down. The power dissipation in the circuit increases with increasing VDD. The graph related to average power consumption is shown in Fig.3. The Power-Delay Product (PDP) of the circuit has also been calculated and shown in Table 2. The average power consumption, gate delay of the CMOS NAND gate has been measured and presented in Table 2. AVERAGE POWER CONSUMPTION, SPEED AND PDP ANALYSIS OF CMOS NAND GATE AT 150 NM CHANNEL LENGTH OF MOS TRANSISTOR This indicates the correct functionality of the circuit. The simulated waveforms as shown in Fog.2 is like the bit patterns according to the truth table of Table.1. However, when all the inputs are at logic “High” output transits to logic “Zero”. As shown in Fig.2, the output is logic “High”, whenever any of the input is at logic “Zero”. The input and output waveforms are shown in Fig.2. For the clarification of the functionality of the CMOS NAND gate, the truth table of the CMOS NAND gate is shown in table1. CLARIFICATION OF FUNCTIONALITY OF CMOS NAND GATEįor the correctness of the design, the netlist of the circuit has been generated and simulated at 150 nm channel length of MOS transistor. The node “A” and “B” are considered as input terminals and node “Y” has been considered as output terminal. Two-bit sources are used for the generation of the input signal. The source terminals of PMOS transistors are connected to power supply voltage (VDD) and source terminal of one of the NMOS transistor is connected to ground. To avoid the body bias effect, body terminal is connected to the source terminal. Two PMOS transistors are connected in parallel in the pull-up network. Two NMOS transistors are connected in series in the pull-down network. The schematic diagram of two input CMOS NAND gate is shown in Fig.1. DESIGN OF TWO INPUT CMOS NAND FUNCTION USING SPICE Context to the low power and high-speed integrated circuit fabrication, the power consumption & delay of the CMOS NAND gate has been measured and reported. Low-power & high-speed circuit design is the recent trends of Integrated Circuit fabrication In this work, the two input CMOS NAND gate has been constructed. Therefore, average power consumption is the summation of switching power, short circuit power and leakage power dissipation. In addition to the switching power, short circuit power and leakage power dissipation are also observed in CMOS circuit. This type of power dissipation is known as switching or dynamic power dissipation. On the other hand, whenever PDN is on, logic “0” is transferred to the output node and some power is dissipated in across the PDN. Whenever, PUN is on then logic “1” is transferred to the output node and during this time some power is dissipated across PUN. The block which is connected between power supply voltage and output is known as pull-up network (PUN) and the block which is connected between the output node and ground is known as the pull-down network (PDN). CMOS design technique is the simplest methodology for integrated circuit design.
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